1. Field of the Invention
The present invention relates to power control for a semiconductor device.
2. Description of the Related Art
As the process becomes finer with advances in semiconductor manufacturing technology, miniaturization of transistor elements has made rapid progress. As a result, the number (the degree of integration) of transistors that can be mounted on a chip with the same area increases, so the circuit scale has expanded to 10 or more times in several recent years. With an increase in circuit scale, the power consumed by the circuit also tends to increase. The power consumed by the circuit includes dynamic power and static power.
The dynamic power means power generated by a current which flows through the transistor due to a signal change. The dynamic power can be reduced by suppressing a signal change, and the clock gating technique of shutting down clock supply to the circuit for a period in which a circuit operation is unnecessary is employed as a measure to reduce the dynamic power.
On the other hand, the static power means power generated by a leak current which flows through the transistor even without a signal change. To reduce the static power, it is effective to keep the power voltage supplied to the transistor low, or shut down voltage supply. Hence, the power shutdown technique aiming at reducing the static power has become prevalent.
Note that an electric power wiring used for power supply to the transistors in the entire chip region will be referred to as a “global wiring” hereinafter, and that used for power supply from the global wiring to the transistors in some circuit blocks will be referred to a “local wiring” hereinafter.
In the power shutdown technique, switches implemented by, for example, transistors are connected between the global wiring and the local wiring of a circuit block to undergo power shutdown to make these two wirings electrically isolable so that the power supply and shutdown are switched by ON/OFF control of the switches as needed. In the circuit block having undergone power shutdown, a leak current disappears, so the consumption of static power due to a leak current can be cut.
Nowadays, by virtue of improvements in material and manufacturing method, a leak current no longer shows a tendency to exponentially increase, unlike the conventional cases, but still keeps a tendency to linearly increase, so the power shutdown technique will continue to play an important role as a method of reducing static power in the future. Also, a circuit block which requires power shutdown in a chip is expected to increase steadily and therefore occupy almost the entire chip after several years.
The charges stored in the capacitance of a circuit block having undergone power shutdown decrease upon removal with time, and disappear eventually. Therefore, to operate a circuit block again after power shutdown, it is necessary to charge the capacitance of the circuit block again. In other words, it is necessary to supply a charge corresponding to the capacitance of the circuit block, thus consuming power upon charging. This power consumption upon charging will be referred to as “charge power” hereinafter. That is, a circuit block in a power shutdown state consumes no static power, but generates charge power every time return to power supply is made.
The number of return operations of power supply per unit time increases in proportion to the number of circuit blocks to undergo power shutdown. In a chip with its entire configuration built by a circuit block to undergo power shutdown, an increase in charge power is more non-negligible than a reduction in static power, and this may inhibit the power reduction effect by the power shutdown technique.
In order to solve this problem, a technique called “charge recycle”, in which charges lost upon discharge after power shutdown in one circuit block are distributed to the capacitance of another circuit block which returns from a power shutdown state to a power supply state. Using this technique, charges lost upon discharge after power shutdown in the conventional cases are recycled in power return to reduce the amount of charges to be supplied to the capacitance at the time of power return, and, in turn, to reduce the charge power.
In the above-mentioned technique, local power supplies in a plurality of circuit blocks are connected to each other via a switch (to be referred to as a “CR switch” hereinafter). The CR switch is switched at the timings of power shutdown and returns to connect or disconnect the local power supplies to or from each other, thereby performing a charge recycle.
The CR switch is switched using the timing measured by simulation before layout of a chip. That is, the switching timing of the CR switch, and the power return timing are always controlled to be constant. However, such timing control operations cannot cope with the case wherein, for example, the timing shifts due, for example, to individual variations of transistors in a chip, which occur upon evolution of technology nodes. Also, power that can be reduced originally may waste as charges cannot be optimally distributed to a capacitance.